Pallavi Reddy Kankar

Pallavi Reddy Kankar

No headline available | Pleasanton, California, United States

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Work Experience

Microsoft

Power and Performance Principal Architect

Thu Jul 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Intel

SoC Power and Performance System Validation Architect

Thu Sep 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Intel

Technologist/Technical Consulting Engineer

Tue Sep 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Intel

AE Champion ,Technical lead and Architect for New Technologies & Modern Standby

Sun Apr 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Intel

ME Firmware debug engineer for OEM Server and Workstation

Sat Jan 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Dec 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Power Management System Validation Engineer

Sun Jan 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Dec 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Layout /Tapeout engineer

Sun Aug 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Aug 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)

Skills

Languages

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